The present invention relates to a semiconductor device, and more specifically to a semiconductor device on which a chip having a plurality of input pads for voltage supply or ground is mounted.
Recently, semiconductor memory devices, in particular, dynamic RAMs have been improved. They are now used in circuits having higher integration and larger capacities. However, charges on and discharges from bit lines connected to these memory cells tend to increase. As a result, the charge/discharge current increases and the potential of the voltage supply or ground fluctuates (referred to as voltage supply noise) due to wire inductance and resistance, thus exerting a harmful influence upon circuit operation speed.
FIGS. 13A to 13C show an internal configuration of a package for a conventional semiconductor device of the dual-in-line package (DIP) type. FIG. 13A is a plan view showing the bonding status; FIG. 13B is a plan view showing a lead frame from which a semiconductor chip is removed; and FIG. 13C is a cross-sectional view taken along the line A--A in FIG. 13A.
As shown in FIG. 13A, major voltage supply lines 1a and 1b are arranged on a wire-bonded semiconductor chip 1 located at the middle portion of a resin sealing body 10. The semiconductor chip 1 is mounted on a die pad 3 of a lead frame by a conductive adhesive (e.g. conductive paste) 2, and bonding pads of the semiconductor chip 1 are connected to lead terminals 4.sub.1 to 4.sub.16 of the lead frame via bonding wires. Further, two tie bars 6 are connected to the die pad 3. These tie bars 6 serve to support the die pad 3 at the frame portion of the lead frame before the chip 1 is sealed by resin. However, these tie bars 6 are cut away from the frame after the chip 1 has been sealed by resin.
In the case shown in FIG. 13A, the pin (lead terminal) 4.sub.1 located at the upper leftmost position is a voltage supply pin. This voltage supply pin is connected to two input pads arranged on the semiconductor chip 1 via bonding wires. One of these two input pads is a voltage supply line la for a main (core) circuit and the other thereof is a voltage supply line 1b for peripheral circuits. Since these voltage supply lines 1a and 1b, divided into two systems, are provided independently inside the semiconductor chip 1, it is possible to prevent voltage supply noise generated by the core circuit due to charge/discharge current through the bit lines from exertion a harmful influence upon the peripheral circuits.
Recently, there exists a tendency such that the semiconductor chip is increased in size but miniaturized in configuration, so that the wires arranged in the semiconductor chip 1 increase in length but decrease in diameter. Therefore, the inductance and resistance of each of the wires (e.g. Al) arranged on the semiconductor chip tend to increase markedly.
As a result, there arises a new problem in that an erroneous operations occur due to charge/discharge current when the circuit is in operation, which has been so far disregarded. As one example, it is known that the potential of the voltage supply or ground fluctuates (referred to as output noise) due to the charge/discharge current caused by an external load capacitance of an output buffer. The above-mentioned fluctuations become further noticable with an increasing number of input/outputs (I/O), thus reducing the circuit operation speed.
In general, almost all voltage supply noise is caused by the inductance component of the lead frame. Conventionally, since the charge/discharge capacitance has required increase, or a high speed switching operation required without reducing the parasitic inductance component of the lead frame, the supply voltage noise and output noise exert a harmful influence upon the chip internal circuits with an increasing capacity of the semiconductor chip.